1. Field of the Invention
This invention relates to integrated circuit (IC) drivers, receivers and their interconnection lines; in particular, this invention relates to VLSI (very large scale integrated) CMOS circuits operating at conventional supply voltage, e.g. 3.3 V, and their interconnections having characteristics of transmission lines.
2. Discussion of the related Art
Complex computer systems are often formed by numerous interconnected VLSI circuits. At very high switching rates, the signal lines interconnecting these VLSI circuits behave as transmission lines. That is, the "edge rate" (or "rise time") of a signal in such an interconnection line is shorter than the signal transit time through the interconnection line. To achieve such a high switching rate, a special driver, which can switch a large current very rapidly, is often used to generate a fast signal. However, in a typical IC package, a pin's relatively large inductance limits how fast a current in that pin can change, and thus limits the switching rate of the signal on the pin. Because of this inductance, an electrical noise, commonly referred to as a "ground bounce," can be generated in the signal whenever a driver on the pin turns on or off rapidly. This inductance may also cause signal ringing in concert with the load capacitance and low driver impedance.
It is known that a fast signal edge driven in an unterminated transmission line can result in a reflection at an end of the transmission line, resulting in a possible overdriving of the receiver circuitry at such end of the transmission line. This reflection is propagated back toward the driver, resulting also in a possible overdrive of the driver circuitry, as well as causing problems at other receivers and drivers along the transmission line. Such overdriving of both the driver and the receiver circuits on a transmission line may cause electrical failure or even physical damage in some cases. Commonly, the reflected signal is also reflected from the driver end towards the receiver end. Thus, reflections are present at both ends of the transmission line. These multiple signal reflections, as they continue to propagate back and forth along the transmission line, prevents the signal from stabilizing at its final value for an extended period of time. An excessive delay in achieving the final signal value may cause the system to fail. To ensure proper system operation, the system's performance is often lowered to accommodate such delay.
In the prior art, to minimize or eliminate the signal reflections discussed above, termination resistors are commonly used. In conventional CMOS circuits, series termination at the driver's output terminal has not proven to be generally practical. This is because, when an external termination is used, the driver impedance is required to have an impractically low value. However, when self-termination (i.e. where the impedance of the driver is the series terminating resistor) is used, inherent process variations in the manufacturing of CMOS circuits very often renders the impedance in the resulting driver to be too high at worst case operating conditions, or too low at best case operating conditions, or both.
Another method used in the prior art to minimize signal reflections is called "parallel termination", which terminates a transmission line at both ends with resistors connected to a terminating voltage. These resistors are each typically chosen to have a resistance equal to the line's characteristic impedance (Z.sub.0), which is, for example, 50-70 ohms in a printed circuit board transmission line. Thus, when operating at typical power supply levels (e.g. 5.0 volts or 3.3 volts), parallel termination used in conventional CMOS or TTL signals consumes significant power and requires very large IC drivers. Additionally, such parallel termination reduces the voltage swing of the signal on the transmission line, thereby reducing the speed at which the signal can be effectively sensed by an input buffer or receiver. For these reasons, termination by resistors is rarely used in the prior art for CMOS and TTL circuitries.
In the prior art, "low swing" methods, such as providing transceivers using either emitter coupled logic (ECL) or GTL (a descriptor coined by Gunning, below), have used proposed. GTL is described in U.S. Pat. No. 5,023,488 to Gunning. These methods offer certain advantages but also have their disadvantages. For example, while GTL offers a low voltage swing and is applicable to CMOS circuitry, ECL is not readily applicable to CMOS circuitry. However, GTL suffers from (i) a potentially serious problem of signal ringing when the driver transistor turns off; (ii) a noise-sensitive low voltage signal swing, which is difficult and slow to translate to the IC operating voltage in the receiver, thus requiring the use of a special power supply and voltage reference; and (iii) incompatibility with existing interface standards, hence limiting its applicability and use.
FIG. 1 illustrates a connection scheme used in the prior art to connect transceivers to a signal bus. In FIG. 1, multiple transceivers, each consisting of a driver (indicated by one of drivers 13a-13h) and a receiver (indicated by the corresponding one of receivers 12a-12h) are connected to signal bus 14. Signal bus 14 is parallel terminated at each end by resistors 15 and 15a to a reference voltage 10, which is typically set at 50% of the operating supply voltage.
Proper termination of signal bus 14 requires matching each of the resistors' impedances to the impedance of signal bus 14. In practice, the effective line impedance can be considerably lower than the characteristic 50 ohms, due to the capacitances of the transceivers connected to signal bus 14. If drivers 13a-13h are driving intermediate points a distance from the ends of the bus, and the signal bus is parallel terminated at both ends with two 50 ohm resistors, each driver ideally would be designed to have an impedance of 25 ohms. Under this scheme, the voltage swing of the signal on the signal bus would range between 25% to 75% of supply voltage (i.e. 0.825 v to 2.475 v on a circuit operating from 3.3 v supply voltage). Signal swing is therefore only one half of the supply voltage (i.e 1.65 v on a circuit operating from a 3.3 v supply voltage). In a high performance system, the receiver is typically designed to recognize a valid signal change after 50% of the signal transition, i.e. the input threshold voltage should be set at 50% of the supply voltage, e.g 1.65 v in a circuit operating from 3.3 v supply voltage. Thus, ideally, in such a system, the noise margin, which is defined as the driver output voltage level minus the receiver input threshold level, is then one quarter of the supply voltage (i.e. +/-825 mv in a circuit operating from a 3.3 v supply voltage).
The factors which affect driver strengths and receiver sensitivities, i.e. the normal variations in the manufacturing process, the ambient operating conditions of the circuit, and the operating voltage, reduce the actual effective operating voltage or signal swing available in the scheme shown in FIG. 1 to considerably less than one half the supply voltage. Such a low effective signal swing considerably reduces noise margins and decreases input receiver performance. Significantly also, the scheme shown in FIG. 1 does not provide TTL-compatible voltage levels.
In addition, the power dissipation in FIG. 1's signal bus 14 is high. Current in signal bus 14 is equal to the reference voltage (V.sub.ref) divided by the net impedance through the resistors 15 and 15a and the driver driving signal bus 14 at the time. Thus, assuming a 50-ohm transmission line and a 3.3 v supply, the current in signal bus 14 is 66 ma with a DC power dissipation of 218 mw. Power dissipated in the driver is 50% of the total, or 109 mw. If signal bus 14 is a 32-bit bus, the total power dissipation in the driver circuits is as high as 32.times.109 mw=3.5 w. Even allowing for a lower average operating duty cycle, the power dissipation in the termination scheme illustrated by signal bus 14 is unacceptable in most applications.
Thus, few CMOS and TTL systems use such parallel resistor terminated lines because of the DC power dissipation. FIG. 2 shows a similar approach, which is more frequently used in CMOS and TTL circuits. To simplify comparison, elements in FIG. 2 which correspond to like elements of FIG. 1 are provided like reference numerals. Unlike FIG. 1, however, signal bus 14 is not terminated by resistors. Instead, signal bus 14 is provided at the ends diodes 17-18 and diodes 17a-18a to clamp the voltages at each end of the transmission line to the supply (16) and ground (19) voltages. With the termination resistors 15 and 15a eliminated, the signal on signal bus 14 reflects from the ends of the signal bus 14. U.S. Pat. No. 4,414,480 to Zasio discloses the use of signal reflections to generate the full swing signals needed to properly switch conventional input buffers. In Zasio's approach, which uses 25-ohm drivers on a 50-ohm line, the initial output signal at an output driver is ideally 50% of supply voltage, or 1.65 v. This initial output signal is then reflected from the far ends of the transmission line to create the final full swing signal.
Thus, the "worst case" total time required to achieve a valid signal level is the complete round trip travel time of the signal from one end of the transmission line to the other and back again. Consequently, the maximum ("worst case") driver impedance to achieve a valid signal is about 50% of the characteristic impedance of the signal line.
In a conventional CMOS process, the minimum ("best case") impedance is in the range of 10% to 15% of the characteristic line impedance. Thus, under "best case" conditions, the initial output signal at the output driver is considerably larger than 50% of the supply voltage. Upon reflection from the ends of the transmission line, the reflected signal is doubled to a value considerably more than the supply voltage. This high voltage not only consumes extra power, but, when sufficiently large, may cause spurious operation (e.g. "latchup") and physically damage the receiver input terminals. To limit such excessive voltages, a transmission line is commonly terminated with diode clamps 17-18 and 17a-18a to the power supply 16 and ground voltage 19. Diodes 17, 17a, 18 and 18a limit signal voltage excursions to within a safe range, but does not reduce power dissipation.
In some applications, the drivers are specifically designed with a very low impedance to guarantee switching on the "incident wave" i.e. before signal reflections occur. Incident wave switching eliminates the need and therefore the time required for the reflected signal to return from the transmission line end. However, the very low impedance required of the driver under incident wave switching is usually impractical in CMOS circuits, thereby limiting the use of incident wave switching to very few CMOS circuits. Furthermore, power dissipation with incident wave switching is high and the attendant low buffer impedance requirement tends to cause undesirable signal ringing. In fact, the time required for a ringing signal to stabilize is often longer than the time saved in driving the transmission line with the "incident wave".
Another technique, described in U.S. Pat. No. 4,450,370 to Davis, replaces a terminating resistor, e.g. as terminating resistor 15 of FIG. 1, by a single active termination. An example of such an active termination is a tristate buffer.
It is desirable to have an interface standard for CMOS circuits. Such interface standard, together with associated circuits that are compatible with existing interface standards (e.g. TTL), is preferably extensible to operate at higher performance levels as needed. Additionally, it is desirable that this CMOS interface standard includes an improved practical transmission line connection and termination scheme, which controls both signal ringing and reflections at a reduced power dissipation requirement.